// CHIP_ID: ADR-2025-NEURO-RTL

Anoop Deekshith Ravikumar

RTL Design · Physical Design · Post-Silicon Validation

VerilogSystemVerilogC++Neuromorphic
● READY | M.S. ECE @ UC Santa Cruz | San Francisco, CA
// Initializing chip renderer...
Get in Touch

Open for Roles &
Collaborations

Whether you're looking for an RTL engineer, a physical design collaborator, or someone who has lived in the post-silicon debug trenches — I'd love to hear from you.

⬡Full-time RTL / PD roles
⬢Research collaborations
◈Neuromorphic / edge AI projects
◇Post-silicon consulting

Goes directly to anoopdeekshith.ece@gmail.com

Contact

Let's Build Silicon Together

Open to RTL Design, Physical Design, and Validation roles

anoopdeekshith.ece@gmail.com
linkedin.com/in/anoopdeekshithr
github.com/AnoopDeekshith
medium.com/@anoopdeekshith
@anoopdeekshith// link to be updated
// San Francisco, CA · Available for full-time roles and research collaborations
// Response time: < 24h
© 2025 Anoop Deekshith Ravikumar — Built with Next.js + GSAP + D3.js// v2.0.0 · RTL-aesthetic portfolio